Description

The PicoTDC is a specially developed 64 channel Time to Digital Converter (TDC) ASIC in 65nm CMOS for use in High Energy Physics (HEP) experiments and similar scientific applications where high rate, very high time resolution single shot time mesurements are required on a large number of channels. It is a succesor to the HPTDC chip that over the last 15 years has been used extensively within HEP and other domains. It is made highly flexible to be adaptable to a large set of different applications:

  • 3ps or 12ps binning with very low jitter (<1ps) and high stability (~1ps).
  • 40MHz reference clock to which all time measurements are locked via PLL and DLL
  • 64 or 32 differential channels.
  • Leading / trialing edge mode or leading edge plus TOT mode.
  • Large on-chip data buffering capability.
  • Option of triggering with programmable latency and time window.
  • Support for overlapping trigger windows.
  • Option of using channel 0 as timing channel and trigger generator channel.
  • 1 or 4 8bit readout ports at 320MHz.
  • 3/12ps resolution test pulse generator
  • I2C control and monitoring interface

Architecture

Presentations - Reports

  • JINST (pdf)
  • TWEPP2019 (pdf)
  • DIRC2019 (pdf)
  • Measurements on latest silicon version (with prototype package) (pdf)

CERN Indico category with PicoTDC meetings (some meetings will have limited access). (link)